Testability of SPP Three-Level Logic Networks in Static Fault Models

Recently introduced, three-level logic Sum of Pseudoproducts (SPP)
forms allow the representation of Boolean functions with much
shorter expressions than standard two-level Sum of Products (SOP)
forms, or other three-level logic forms.

In this paper the testability of circuits derived from SPPs is
analyzed. We study testability under static Fault Models (FMs),
i.e., the Stuck-At Fault Model (SAFM) and the Cellular Fault Model
(CFM). For SPP networks several minimal forms can be considered.
While full testability can be proved in the SAFM for some forms,
SPP networks in the CFM are shown to contain redundancies.

Finally, we propose a method for transforming non-testable
networks into testable ones. Experimental results are given to
demonstrate the efficiency of the approach.